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#1 2009-03-24 10:41:46
- edo512
- Contributor
- Registered: 2008-10-07
- Posts: 103
loread sample period
A simple question but I have not been able to get a proper answer reading the source code: how do I translate the plot sample period/duration into actual milliseconds in 125kHz and 134kHz mode?
Ed
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#2 2009-03-24 21:21:19
- henrym97
- Contributor
- From: North America
- Registered: 2009-01-23
- Posts: 18
Re: loread sample period
I think the answer would be in the FPGA code...
In general the raw sample rate will be at whatever rate the ADC (IC8) is being clocked at on pin 12. This signal comes from the FPGA (IC1) pin 46, so I assume it changes based on mode (e.g. slower sample rate for LF operation). Assuming the FPGA doesn't decimate or throw away samples, the plot sample period should be the period of the ADC clock signal.
Of course the FPGA author should clear this up for sure...
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#3 2015-01-13 16:37:14
- iceman
- Administrator
- Registered: 2013-04-25
- Posts: 9,537
- Website
Re: loread sample period
I'm impressed, +1 for bumping a 5year thread.
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